1. Field of the Invention
The present invention relates generally to analog-to-digital converting circuits and more particularly to analog-to-digital converting circuits using a two-step, time shift error-compensating technique to achieve high resolution.
2. Art Background
A typical data-acquisition system receives signals from a variety of different sources and transmits these signals in suitable form to a computer or a communication channel. In such systems, a multiplexer is usually employed to select each signal in sequence, and then the analog information is converted into a constant voltage over the gating-time interval by means of a sample-and-hold system. The constant output of the sample-and-hold may then be converted to a digital signal by means of an analog-to-digital (A/D) converter for digital transmission. Therefore, a basic A/D converting circuit would require a sample-and-hold element and an A/D converting element to convert an analog signal into a series of digital signals.
In the field of high resolution analog-to-digital conversion, the A/D conversion is usually developed with two step conversion techniques. FIG. 1 shows a typical A/D converter structure in the prior art. As shown in FIG. 1, a train of analog input signals is first applied through a sample-and-hold mechanism 10 to produce a train of discrete signals, which are then converted to digital signals ("coarse signal") and stored in a digital signal processor for processing. The size of the digital signal n is dependent upon the A/D converter 11.
To detect conversion errors, the same digital signals are then converted back to analog signals through a D/A converter 12 with its output signals applied to the negative input of a subtracter unit 13. To adjust for the timing difference, the output from the sample-and-hold mechanism 10 is delayed through a delay mechanism 16 with its output applied to the positive input of a subtracter unit 13. The difference of these two signals, which represents the error from the conversion, is then converted in another A/D converter 14 under the same conversion rate to produce another n bits of digital signals ("fine signal") and stored in a digital signal processor 15 for processing.
An error-compensating circuit such as a digital signal processor 15 (DSP) is then used to compensate the conversion error resulted from the non-linearity of the circuit by comparing between the coarse and the fine signals. The least significant bit (LSB) of the signal from the coarse A/D converter and the most significant bit (MSB) of the signal from the fine A/D converter are compared and the conversion error is corrected by the DSP. The desired digital output contains (2n-1) bits, where n is dependent upon the A/D converter. As will be seen in the following description, the presently claimed invention employs only one set of A/D and D/A components to achieve the same high resolution A/D conversion.